Three dimensional structure memory

ABSTRACT

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to stacked integrated circuit memory.

2. State of the Art

Manufacturing methods for increasing the performance and decreasing thecost of electronic circuits, nearly without exception, are methods thatincrease the integration of the circuit and decrease its physical sizeper equivalent number of circuit devices such as transistors orcapacitors. These methods have produced as of 1996 microprocessorscapable of over 100 million operations per second that cost less than$1,000 and 64 Mbit DRAM circuits that access data in less than 50 ns andcost less than $50. The physical size of such circuits is less than 2cm^(.) Such manufacturing methods support to a large degree the economicstandard of living in the major industrialized countries and will mostcertainly continue to have significant consequences in the daily livesof people all over the world.

Circuit manufacturing methods take two primary forms: processintegration and assembly integration. Historically the line betweenthese two manufacturing disciplines has been clear, but recently withthe rise in the use of MCMs (Multi-Chip Modules) and flip-chip dieattach, this clear separation may soon disappear. (The predominate useof the term Integrated Circuit (IC) herein is in reference to anIntegrated Circuit in singulated die form as sawed from a circuitsubstrate such as s semiconductor wafer versus, for example, anIntegrated Circuit in packaged form.) The majority of ICs when ininitial die form are presently individually packaged, however, there isan increasing use of MCMs. Die in an MCM are normally attached to acircuit substrate in a planar fashion with conventional IC die I/Ointerconnect bonding methods such as wire bonding, DCA (Direct ChipAttach) or FCA (Flip-Chip Attach).

Integrated circuit memory such as DRAM, SRAM, flash EPROM, EEPROM,Ferroelectric, GMR (Giant MagnetoResistance), etc. have the commonarchitectural or structural characteristic of being monolithic with thecontrol circuitry integrated on the same die with the memory arraycircuitry. This established (standard or conventional) architecture orcircuit layout structure creates a design trade-off constraint betweencontrol circuitry and memory array circuitry for large memory circuits.Reductions in the fabrication geometries of memory cell circuitry hasresulted in denser and denser memory ICs, however, these higher memorydensities have resulted in more sophisticated control circuitry at theexpense of increased area of the IC. Increased IC area means at leasthigher fabrication costs per IC (fewer ICs per wafer) and lower ICyields (fewer working ICs per wafer), and in the worst case, an ICdesign that cannot be manufactured due to its non-competitive cost orunreliable operation.

As memory density increases and the individual memory cell sizedecreases more control circuitry is required. The control circuitry of amemory IC as a percentage of IC area in some cases such as DRAMsapproaches or exceeds 40%. One portion of the control circuitry is thesense amp which senses the state, potential or charge of a memory cellin the memory array circuitry during a read operation. The sense ampcircuitry is a significant portion of the control circuitry and it is aconstant challenge to the IC memory designer to improve sense ampsensitivity in order to sense ever smaller memory cells while preventingthe area used by the sense amp from becoming too large.

If this design constraint or trade-off between control and memorycircuits did not exist, the control circuitry could be made to performnumerous additional functions, such as sensing multiple storage statesper memory cell, faster memory access through larger more sensitivesense amps, caching, refresh, address translation, etc. But thistrade-off is the physical and economic reality for memory ICs as theyare presently made by all manufacturers.

The capacity of DRAM circuits increases by a factor of four from onegeneration to the next; e.g. 1 bit, 4 bit, 16 Mbit and 64 Mbit DRAMs.This four times increase in circuit memory capacity per generation hasresulted in larger and larger DRAM circuit areas. Upon introduction of anew DRAM generation the circuit yields are too low and, therefore, notcost effective for high volume manufacture. It is normally several yearsbetween the date prototype samples of a new DRAM generation are shownand the date such circuits are in volume production.

Assembling die in a stacked or three dimensional (3D) manner isdisclosed in U.S. Pat. No. 5,354,695 of the present inventor,incorporated herein by reference. Furthermore, assembling die in a 3Dmanner has been attempted with regard to memory. Texas Instruments ofDallas Tex., Irvine Sensors of Costa Mesa Calif. and Cubic MemoryCorporation of Scotts Valley Calif. have all attempted to producestacked or 3D DRAM products. In all three cases, conventional DRAMcircuits in die form were stacked and the interconnect between each DRAMin the stack was formed along the outside surface of the circuit stack.These products have been available for the past several years and haveproved to be too expensive for commercial applications, but have foundsome use in space and military applications due to their small physicalsize or footprint.

The DRAM circuit type is referred to and often used as an example inthis specification, however, this invention is clearly not limited tothe DRAM type of circuit. Undoubtedly memory cell types such as EEPROMs(Electrically Erasable Programmable Read Only Memories), flash EPROM,Ferroelectric, GMR Giant Magneto Resistance or combinations (intra orinter) of such memory cells can also be used with the present ThreeDimensional Structure (3DS) methods to form 3DS memory devices.

The present invention furthers, among others, the following objectives:

1. Several-fold lower fabrication cost per megabyte of memory thancircuits conventionally made solely with monolithic circuit integrationmethods.2. Several-fold higher performance than conventionally made memorycircuits.3. Many-fold higher memory density per IC than conventionally madememory circuits.4. Greater designer control of circuit area size, and therefore, cost.5. Circuit dynamic and static self-test of memory cells by an internalcontroller.6. Dynamic error recovery and reconfiguration.7. Multi-level storage per memory cell.8. Virtual address translation, address windowing, various addressfunctions such as indirect addressing or content addressing, analogcircuit functions and various graphics acceleration and microprocessorfunctions.

SUMMARY OF THE INVENTION

The present 3DS memory technology is a stacked or 3D circuit assemblytechnology. Features include:

1. Physical separation of the memory circuits and the control logiccircuit onto different layers;2. The use of one control logic circuit for several memory circuits;3. Thinning of the memory circuit to less than about 50 μm in thicknessforming a substantially flexible substrate with planar processed bondsurfaces and bonding the circuit to the circuit stack while still inwafer substrate form; and4. The use of fine-grain high density inter layer vertical busconnections.

The 3DS memory manufacturing method enables several performance andphysical size efficiencies, and is implemented with establishedsemiconductor processing techniques. Using the DRAM circuit as anexample, a 64 Mbit DRAM made with a 0.25 μm process could have a diesize of 84 mm², a memory area to die size ratio of 40% and a access timeof about 50 ns for 8 Mbytes of storage; a 3DS DRAM IC made with the same0.25 μm process would have a die size of 18.6 mm², use 17 DRAM arraycircuit layers, a memory area to die size ratio of 94.4% and an expectedaccess time of less than 10 ns for 64 Mbytes of storage. The 3DS DRAM ICmanufacturing method represents a scalable, many-fold reduction in thecost per megabyte versus that of conventional DRAM IC manufacturingmethods. In other words, the 3DS memory manufacturing method represents,at the infrastructure level, a fundamental cost savings that isindependent of the process fabrication technology used.

BRIEF DESCRIPTION OF THE DRAWING

The present invention may be further understood from the followingdescription in conjunction with the appended drawing. In the drawing:

FIG. 1 a is a pictorial view of a 3DS DRAM IC manufactured with Method Aor Method B and demonstrating the same physical appearance of I/O bondpads as a conventional IC die;

FIG. 1 b is a cross-sectional view of a 3DS memory IC showing the metalbonding interconnect between several thinned circuit layers;

FIG. 1 c is a pictorial view of a 3DS DRAM IC stack bonded andinterconnected face-down onto a larger conventional IC or another 3DSIC;

FIG. 2 a is a diagram showing the physical layout of a 3DS DRAM arraycircuit block with one data-line set of bus lines, i.e. one port;

FIG. 2 b is a diagram showing the physical layout of a 3DS DRAM arraycircuit block with two sets of data-line bus lines, i.e. two ports;

FIG. 2 c is a diagram showing the physical layout of a portion of anexemplary memory controller circuit;

FIG. 3 is a diagram showing the physical layout of a 3DS DRAM arraycircuit showing partitions for sixty-four (64) 3DS DRAM array blocks;

FIG. 4 is a cross-sectional view of a generic 3DS verticalinterconnection or feed-through in a thinned substrate;

FIG. 5 is a diagram showing the layout of a 3DS memory multiplexer fordown-selecting gate-line read or write selection.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 a and FIG. 1 b, the 3DS (Three DimensionalStructure) memory device 100 is a stack of integrated circuit layerswith fine-grain vertical interconnect between all circuit layers. Theterm fine-grain inter-layer vertical interconnect is used to meanelectrical conductors that pass through a circuit layer with or withoutan intervening device element and have a pitch of nominally less than100 μm and more typically less than 10 μm, but not limited to a pitch ofless than 2 m, as best seen in FIG. 2 a and FIG. 2 b. The fine-graininter-layer vertical interconnect also functions to bond together thevarious circuit layers. As shown in FIG. 1 b, although the bond andinterconnect layers 105 a, 105 b, etc., are preferably metal, othermaterial may also be used as described more fully hereinafter.

The pattern 107 a, 107 b, etc. in the bond and interconnect layers 105a, 105 b, etc. defines the vertical interconnect contacts between theintegrated circuit layers and serves to electrically isolate thesecontacts from each other and the remaining bond material; this patterntakes the form of either voids or dielectric filled spaces in the bondlayers.

The 3DS memory stack is typically organized as a controller circuit 101and some number of memory array circuit layers 103, typically betweennine (9) and thirty-two (32), but there is no particular limit to thenumber of layers. The controller circuit is of nominal circuit thickness(typically 0.5 mm or greater), but each memory array circuit layer is athinned and substantially flexible circuit with net low stress, lessthan 50 μm and typically less than 10 μm in thickness. Conventional I/Obond pads are formed on a final memory array circuit layer for use withconventional packaging methods. Other metal patterns may be used such asinsertion interconnection (disclosed in U.S. Pat. Nos. 5,323,035 and5,453,404 of the present inventor), DCA (Direct Chip Attach) or FCA(Flip-Chip Attach) methods.

Further, the fine grain inter-layer vertical interconnect can be usedfor direct singulated die bonding between a 3DS memory die and aconventional die (wherein the conventional die could be the controllercircuit as shown in FIG. 1 c) or a 3DS memory die and another 3DS memorydie; it should be assumed that the areas (sizes) of the respective diceto be bonded together can vary and need not be the same. Referring moreparticularly to FIG. 1 c, a 3DS DRAM IC stack 100 is bonded andinterconnected face-down onto a larger conventional IC or another 3DS IC107. Optionally the 3DS stack 100 can be composed of only DRAM arraycircuits with the DRAM controller circuitry as part of the larger die.If the DRAM controller circuitry is part of the larger die, thenfine-grain vertical bus interconnect would be required (at the face 109of the 3DS DRAM IC stack 100) to connect the 3DS DRAM array circuit tothe DRAM controller, otherwise larger grain conventional interconnectioncould be incorporated (patterned) into the planarized bond layer.

As shown in FIG. 3, each memory array circuit layer includes a memoryarray circuit 300 composed of memory array blocks 301 (nominally lessthan 5 mm² in area) and each block is composed of memory cells (in muchthe same manner as the cell array of a DRAM or EEPROM circuit), busingelectrodes, and—at the option of the designer—enabling gates forselection of specific rows or columns of the memory array. Thecontroller circuit is composed of sense amps, address, control and drivelogic that would normally be found at the periphery of a typical memorycircuit of monolithic design such as in a conventional DRAM.

Fine-grain busing vertically connects the controller independently toeach memory array layer such that the controller can provide drive(power) or enable signals to any one layer without affecting the stateof any of the other layers. This allows the controller to test, read orwrite independently each of the memory circuit layers.

FIG. 2 a and FIG. 2 b show examples of layouts of possible blocks of amemory array such as the block 301 of FIG. 3. Although only a portion ofthe block is shown, in the illustrated embodiment, the blocks exhibitbilateral symmetry such that the layout of the complete block may beascertained from the illustrated portion. Abbreviations “T”, “L”, and“TL” are used following various reference numerals to indicate “Top”,“Left” and “Top-Left,” respectively, implying corresponding elements notshown in the figure. Referring to FIG. 2 a, a core portion 200 of theblock is composed of a “sea” of memory cells. Logically, the aggregationof memory cells may be subdivided into “macrocells” 201 each containingsome number of memory cells, e.g. an 8×8 array of 64 memory cells. Atthe periphery of the core is formed fine-grain vertical interconnectcomprising inter-layer bond and bus contact metallizations 400,described in greater detail hereinafter with reference to FIG. 4. Thefine-grain vertical interconnect includes I/O power and ground bus lines203TL, memory circuit layer selects 205T, memory macro cell columnselects 207T, data lines 209L, and gate-line multiplexer (“mux”) selects209TL. Gate-line multiplexers 211T are, in the illustrated embodiment,4:1 multiplexers used to select one of four columns within an eight-widememory macro cell column. Corresponding bottom-side 4:1 multiplexerscombine with the topside multiplexers 211T to form equivalent 8:1multiplexers for selecting a single gate-line from aneight-gate-line-wide memory macro cell column.

One implementation of a 4:1 gate-line bus muliplexer 500 is shown inFIG. 5. Gate-line enables 209TL′ (formed in a Metal-1 layer, forexample) control transistors 501 a through 501 d, respectively. Coupledto the transistors are respective gate lines 503 a through 503 d. Alsopartly visible are gate-lines 505 a through 505 d which are coupled to acorresponding 4:1 multiplexer (not shown). When one of the gate-lineenables is active, the corresponding gate-line is coupled to an outputline 507 of the multiplexer (formed in a Metal-2 layer, for example).The output line is connected to one or more vertical bus connectsthrough a line 509 (formed in a Metal-3 layer and corresponding to metalcontact 400 of vertical bus interconnect, for example) and tungstenplugs 511 and 513. The tungsten plug 513 joins the line 509 to avertical interconnect (not shown).

Referring again to FIG. 2 a, in the case of a memory circuit layer, thelayer may also include output line enables (gates) from controller layerenable signals 205T, for which I/O enables (gates) 213 may be provided.

Note that at the memory layer level, each memory block 301 iselectrically isolated from every other memory block 301. Accordingly,the yield probability for each memory block is independent.

Additional read/write ports can be added as can additional gate-linevertical interconnections; additional vertical interconnection can beused in a redundant manner to improve vertical interconnect yield. The3DS memory circuit can be designed to have one or more data read andwrite bus port interconnections. Referring to FIG. 2 b, a memory block301′ is shown as having a port P₀, (209L) and a further port P₁ (209L′).The only limitation on the number of vertical interconnections is theoverhead such vertical interconnections impose on the cost of thecircuit. The fine-grain vertical interconnect method allows thousands ofinterconnects per block at an increase in die area of only a fewpercent.

As an example, the overhead of the vertical interconnect shown in FIG. 2b for a DRAM memory block of 4 bits with two read/write ports andimplemented in 0.35 cm or 0.15 μm design rules consists of approximately5,000 connections and is less than 6% of the total area of the memoryarray block. Therefore, the vertical interconnect overhead for eachmemory array circuit layer in the 3DS DRAM circuit is less than 6%. Thisis significantly less than that presently experienced in monolithic DRAMcircuit designs where the percentage of non-memory cell area can exceed40%. In a completed 3DS DRAM circuit the percentage of non-memory cellarea is typically less than 10% of the total area of all circuits in thestacked structure.

The 3DS memory device decouples control functions that normally would befound adjacent the memory cells of monolithic memory circuits andsegregates them to the controller circuit. The control functions, ratherthan occurring on each memory array layer as in conventional memory ICs,occur only once in the controller circuit. This creates an economy bywhich several memory array layers share the same controller logic, andtherefore, lowers the net cost per memory cell by as much as a factor oftwo versus conventional memory design.

The segregation of the control functions to a separate controllercircuit allows more area for such functions (i.e., an area equal to thearea one or several of the memory array blocks). This physicalsegregation by function also allows fabrication process segregation ofthe two very different fabrication technologies used for the controllogic and the memory array, again realizing additional fabrication costsavings versus the more complicated combined logic/memory fabricationprocess used for conventional memory. The memory array can also befabricated in a process technology without consideration of the processrequirements of control logic functions. This results in the ability todesign higher performance controller functions at lower cost than is thecase with present memory circuits. Furthermore, the memory array circuitcan also be fabricated with fewer process steps and nominally reducememory circuit fabrication costs by 30% to 40% (e.g., in the case of aDRAM array, the process technology can be limited to NMOS or PMOStransistors versus CMOS).

Hence, although bonding of sufficiently planar surfaces of a memorycontroller substrate and a memory array substrate using thermaldiffusion metal bonding is preferred, in the broader aspects of thepresent invention, the invention contemplates bonding of separate memorycontroller and memory array substrates by any of various conventionalsurface bonding methods, such as anisotropically conductive epoxyadhesive, to form interconnects between the two to provide random accessdata storage.

Referring to FIG. 2 c, the layout of a portion of an exemplary memorycontroller circuit is shown. The inter-layer bond and bus contactmetallization has the same pattern as previously described in relationto FIG. 2 a. Instead of a sea of memory cells, however, there isprovided memory controller circuitry including, for example, sense ampsand data line buffers 215. Because of the increased availability of diearea, multi-level logic may be provided in conjunction with the senseamps and data line buffers 215. Also shown are address decode, gate-lineand DRAM layer select logic 217, refresh and self-test logic 219, ECClogic 221, windowing logic 223, etc. Note that self-test logic, ECClogic, and windowing logic are provided in addition to functionsnormally found within a DRAM memory controller circuit. Depending on diesize or the number of controller circuit layers used, any of numerousother functions may also be provided including, for example, virtualmemory management, address functions such as indirect addressing orcontent addressing, data compression, data decompression, audioencoding, audio decoding, video encoding, video decoding, voicerecognition, handwriting recognition, power management, databaseprocessing, graphics acceleration functions, microprocessor functions(including adding a microprocessor substrate), etc.

The size of the 3DS memory circuit die is not dependent on the presentconstraint of containing the necessary number of memory cells andcontrol function logic on one monolithic layer. This allows the circuitdesigner to reduce the 3DS circuit die size or choose a die size that ismore optimal for the yield of the circuit. 3DS memory circuit die sizeis primarily a function of the size and number of memory array blocksand the number of memory array layers used to fabricate the final 3DSmemory circuit. (The yield of a nineteen (19) layer, 0.25 μm process 3DSDRAM memory circuit may be shown to be greater than 90% as describedbelow.) This advantage of selecting the 3DS circuit die size enables anearlier first production use of a more advanced process technology thanwould normally be possible for conventional monolithic circuit designs.This, of course, implies additional cost reductions and greaterperformance over the conventional memory circuits.

3DS Memory Device Fabrication Methods

There are two principal fabrication methods for 3DS memory circuits. Thetwo 3DS memory fabrication methods, however, have a common objectivewhich is the thermal diffusion metal bonding (also referred to asthermal compression bonding) of a number of circuit substrates onto arigid supporting or common substrate which itself may optionally also bea circuit component layer.

The supporting or common substrate can be a standard semiconductorwafer, a quartz wafer or a substrate of any material composition that iscompatible with the processing steps of the 3DS circuit, the operationof the circuit and the processing equipment used. The size and shape ofthe supporting substrate is a choice that best optimizes availablemanufacturing equipment and methods. Circuit substrates are bonded tothe supporting substrate and then thinned through various methods.Circuit substrates may be formed on standard single crystalsemiconductor substrates or as polysilicon circuits formed on anappropriate substrate such as silicon or quartz. Polysilicon transistorcircuits have the important cost saving option of incorporating aparting layer (film) that allows the substrate upon which thepolysilicon circuits are formed to be released and reused. Polysilicontransistor or TFTs (Thin Film Transistor) devices are widely used, andneed not be made solely from silicon.

The various circuit layers of the 3DS memory circuit are bonded togetherby use of thermal diffusion of two metal surfaces, typically aluminum.The surface of the circuits to be bonded are smooth and sufficientlyplanar as is the case with the surface of an unprocessed semiconductorwafer or a processed semiconductor wafer that has been planarized withthe CMP (Chemical Mechanical Processing) method with a surface planarityof less than 1 μm and preferably less than 1,000 Å over at least thearea of the surface of the circuit (formed on the substrate) to bebonded. The metal bonding material on the surfaces of the circuits to bebonded are patterned to be mirror images of each other and to define thevarious vertical interconnect contacts as indicated in FIG. 2 a, FIG. 2b, FIG. 2 c and FIG. 5. The step of bonding two circuit substratesresults in simultaneously forming the vertical interconnection betweenthe two respective circuit layers or substrates.

The thermal diffusion bonding of the circuit layers takes placepreferably in an equipment chamber with controlled pressure andatmospheric components such as N₂ with little H₂O and O₂ content. Thebonding equipment aligns the patterns of the substrates to be bonded,presses them together with a set of programmed pressures and at one ormore temperatures for a period of time as required by the type of metalused as the bonding material. The thickness of the bonding material isnominally in a range of 500 Å to 15,000 Å or greater with a preferredthickness of 1,500 Å. The initial bonding of the substrates ispreferably done at lower than standard pressure such as a negativepressure between 1 torr and 740 torr depending on the design of the bondpattern. This can leave an interior negative pressure between thebonding surfaces once external atmospheric pressure is returned whichfurther assists in the formation of the bond and enhances thereliability of the bond.

The preferred bonding material is pure aluminum or an alloy of aluminum,but it is not limited to aluminum and may include, for example, suchmetals as Sn, Ti, In, Pb, Zn, Ni, Cu, Pt, Au or alloys of such metalsthat provide acceptable surface bond diffusion capabilities atacceptable temperatures and forming periods. The bonding material is notlimited to metal, and could be a combination of bonding materials, suchas highly conductive polysilicon, some of which are non-conducting suchas silicon dioxide, and the foregoing exemplary types of bond materialchoices should not be considered to be limitations on how the circuitlayers can be bonded.

In the case where metal bond materials form a native surface oxide thateither inhibits the forming of a satisfactory bond or may increase theresistance in the vertical interconnections formed by the bond, theoxide should be removed. The bonding equipment provides an oxidereduction capability such that bonding surfaces of the bond material arerendered without native surface oxide. The methods of forming gasatmospheres for the reduction of surface oxides are well known, andthere arc other methods for removing the native oxide such as sputteretching, plasma etching or ion mill etching. In the case where aluminumis used as the bonding material, it is preferred that the thin nativealuminum oxide film of approximately 40 Å on the bonding surfaces beremoved prior to bonding.

The thinned (substantially flexible) substrate circuit layers of the 3DSmemory circuit are typically memory array circuits, however, the thinnedsubstrate circuit layers are not limited to memory circuits. Othercircuit layer types can be controller circuits, non-volatile memory suchas EEPROM, additional logic circuitry including microprocessor logic andapplication specific logic functions such as those that support graphicor database processing, etc. The selection of such circuit layer typesfollows from the functional requirements of the design of the circuitand is not limited by the 3DS memory fabrication process.

The thinned (substantially flexible) substrate circuit layers arepreferably made with dielectrics in low stress (less than 5×10⁸dynes/cm²) such as low stress silicon dioxide and silicon nitridedielectrics as opposed to the more commonly used higher stressdielectrics of silicon oxide and silicon nitride used in conventionalmemory circuit fabrication. Such low stress dielectrics are discussed atlength in U.S. Pat. No. 5,354,695 of the present inventor, incorporatedherein by reference. The use of dielectrics with conventional stresslevels could be used in the assembly of a 3DS DRAM circuit, however, ifmore than a few layers comprise the stacked assembly, each layer in theassembly will have to be stress balanced so that the net stress of thedeposited films of a layer is less than 5×10⁸ dynes/cm². The use ofintrinsically low stress deposited films is the preferred method offabrication versus the use of the method where the stress ofindividually deposited films are not equal but are deposited to create anet balanced lower stress.

Method A, 3DS Memory Device Fabrication Sequence

This fabrication sequence assumes that several circuit layers will bebonded to a common or support substrate and subsequently thinned inplace. An example of a resulting 3DS memory circuit is shown in FIG. 1a.

1. Align and bond to the common substrate the topside of a secondcircuit substrate.

2A. Grind the backside or exposed surface of the second circuitsubstrate to a thickness of less than 50 μm and then polish or smooththe surface. The thinned substrate is now a substantially flexiblesubstrate.

Optionally an etch stop may be incorporated in the second substrate fromless than a micron to several microns below the semiconductor surfaceprior to device fabrication. This etch stop can be an epitaxially formedfilm such as GeB (described in U.S. Pat. Nos. 5,354,695 and 5,323,035 ofthe present inventor, incorporated herein by reference) or a low densityimplanted layer of O₂ or N₂ to form a buried oxide or nitride barrieretch stop layer just below the device layer on the topside of the secondsubstrate. After a preliminary grinding of a significant portion of thebackside of the substrate, the remaining portion of the backside of thesecond substrate is then selectively etched in a chemical bath whichstops on the surface of the eptiaxial or implanted layer. Subsequentpolishing and RIE steps as necessary can then be used to complete thethinning of the second substrate.

Alternately, a parting layer such as H₂ implanted into the topsidesurface of the second substrate prior to device fabrication can be usedwith a thermal step to crack off the majority of the backside of thesecond substrate, allowing its reuse.

2B. The second substrate may alternatively be a circuit formed ofpolysilicon transistors or TFTs over a parting layer such as aluminum,titanium, A1As, KBr, etc. which can be activated by a specific chemicalrelease agent. The backside of the second substrate is then removed uponactivating (dissolving) the release layer and followed as needed byinterconnect semiconductor processing steps.

3. Process the thinned backside of the second substrate to form verticalinterconnections such as that shown in FIG. 4 with the bonded surfaceside of the second substrate. The backside processing typicallycomprises conventional semiconductor processing steps of dielectric andmetal deposition, lithography and RIE, the order of which can vary to agreat degree. The completion of the backside processing will also resultin a patterned metal layer that is similar to the topside bond materialpattern to facilitate the subsequent bonding of an additional circuitsubstrate, a terminal pattern such as a conventional I/O IC bond pad(wire bonding) pattern, a pattern for thermal diffusion bonding of the3DS memory circuit to another die (either another 3DS circuit or aconventional die), or a pattern for insertion interconnection,conventional DCA (Direct Chip Attach) or FCA (Flip-Chip Attach).

Referring more particularly to FIG. 4, during the fabrication of activecircuit devices, an oxide mask 401 is thermally grown or deposited.Vertical bus contacts 403 are then formed, for example from highly-dopedpolysilicon coincident with a polysilicon gate forming step.Alternatively, contact 403 may be formed of metal. Conventional DRAMinterconnect structures 410 are then formed using conventionalprocessing. The DRAM interconnect may include an internal pad 405. The“DRAM processed” portion 420 of the wafer includes various dielectricand metal layers. A final passivation layer 407 is deposited, afterwhich vias 409 are formed. Conventional CMP processing is then used toobtain a planar surface 411. Contacts 413 and bond surfaces not shownare then patterned in a top-most metal layer (e.g, Metal-3).

After bonding and thinning of the backside of the second substrate toabout 1-8 μm of silicon (or other semiconductor) substrate 415,feed-throughs 417 are then formed in registration with the contacts 403.A passivation layer 419 and contacts 421 are then formed. The contacts421 may be formed so as to form a mirror image of the contacts 413,allowing for the bonding of further wafers.

4. If another circuit layer is to be bonded to the 3DS circuit stack,steps 1-3 are repeated.

5A. The circuits of the finished 3DS memory substrate are thenconventionally sawed into die (singulated), resulting in a circuit ofthe type shown in FIG. 1 a, and packaged as would be the case withconventional integrated circuits.

5B. The circuits of the finished 3DS memory substrate are thenconventionally sawed and then individually aligned and thermal diffusionbonded (metal pattern down) to the surface of a second (conventional IC)die or MCM substrate in a manner similar to that used in the bonding ofthe circuit substrates of step 1 above. (The conventional die or MCMsubstrate may have a larger area than the 3DS memory substrate and mayinclude a graphics controller, video controller or microprocessor, suchthat the 3DS becomes embedded as part of another circuit.) This finalbonding step typically incorporates a fine-grain interconnect betweenthe 3DS memory circuit and the die or MCM substrate, but could also usea conventional interconnect pattern. Further, a 3DS memory circuit canbe bonded face up to a conventional IC in die form or MCM substrate andwire bonding used to form conventional I/O interconnections.

Method B, 3DS Memory Device Fabrication Sequence

This fabrication sequence assumes that a circuit substrate will first bebonded to a transfer substrate, thinned and then bonded to a commonsubstrate as a layer of the circuit stack. The transfer substrate isthen released. This method has the advantage over Method A of allowingsubstrates to be thinned prior to being bonded to the final circuitstack and allows for simultaneous thinning and vertical interconnectprocessing of substrate circuit layers.

1. Bond to a transfer substrate a second circuit substrate using arelease or parting layer. A transfer substrate may have high toleranceparallel surfaces (TTV or Total Thickness Variance of less than 1 μm)and may be perforated with an array of small holes to assist the partingprocess.

The parting layer can be a blanket deposition of a bonding metal.Precise alignment of the surfaces is not required.

2. Perform step 2A or 2B of Method A.

3. Process the backside of the second substrate to form interconnectionswith the bonded topside surface of the second substrate as shown in FIG.4. The backside processing typically comprises conventionalsemiconductor processing steps of dielectric and metal deposition,lithography and RIE, the order of which can vary to great degree. Thecompletion of the backside processing will also result in a patternedmetal layer that is similar to the bond material pattern of the commonsubstrate to facilitate the subsequent bonding of an additional circuitlayer.

4. Bond the second circuit to a common or support substrate (3DS stack)and release the transfer substrate by activating the parting layerbetween it and the second circuit.

5. Process the now exposed topside of the second substrate to forminterconnections for subsequent substrate bonding or a terminal patternfor conventional I/O bonding (wire bonding) pad pattern, a pattern forthermal diffusion bonding of the 3DS memory circuit to another die(either another 3DS circuit or a conventional die), or a pattern forconventional insertion interconnect, DCA (Direct Chip Attach) or FCA(Flip-Chip Attach). If another circuit layer is to be bonded to the 3DScircuit stack, steps 1 through 4 are repeated.

6. Perform step 5A or 5B of Method A.

3DS Memory Device Yield Enhancement Methods

The 3DS circuit may be considered a vertically assembled MCM (Multi-ChipModule) and as with an MCM the final yield is the product of the yieldprobabilities of each component circuit (layer) in the completed 3DScircuit. The 3DS circuit uses several yield enhancement methods that aresynergistic in their combined usage within a single memory IC. The yieldenhancement methods used in the 3DS memory circuit include small memoryarray block size, memory array block electrical isolation throughphysically unique or separate vertical bus interconnections, intramemory array block gate-line sparing, memory array layer sparing(inter-block gate-line sparing), controller sparing and ECC (ErrorCorrecting Codes). The term sparing is used to mean substitution by aredundant element.

The selected size of the memory array block is the first component inthe yield equation for the 3DS memory circuit. Each memory array blockis individually (uniquely) accessed and powered by the controllercircuit and is physically independent of each and every other memoryarray block including those on the same memory array layer in additionto those on a different memory array layer. The size of the memory arrayblock is typically less than 5 mm² and preferably less than 3 mm², butis not limited to a specific size. The size of memory array block, thesimplicity of its NMOS or PMOS fabrication process and its physicalindependence from each of the other memory array blocks, for nearly allproduction IC processes, provides a conservatively stated nominal yieldof greater than 99.5%. This yield assumes that most point defects in thememory array block such as open or shorted interconnect lines or failedmemory cells can be spared (replaced) from the intra-block orinter-block set of redundant gate-lines. Major defects in a memory arrayblock which render the complete memory array block unusable result inthe complete sparing of the block from a redundant memory array layer orthe rejection of the 3DS circuit.

In the example of a 3DS DRAM circuit the yield of a stack of memoryarray blocks is calculated from the yield equationYs=((1−(1−P_(Y))²)^(n))_(b), where n is the number DRAM array layers, bis the number of blocks per DRAM array and P_(y) is the effective yield(probability) of a DRAM array block less than 3 mm² in area. Assuming aDRAM array block redundancy of 4% for gate-lines in the DRAM array blocklines and one redundant DRAM array layer, and assuming further that thenumber of blocks per layer is 64, the number of memory array layers inthe stack is 17 and the effective value for Py is 0.995, then the stackyield Ys for the complete memory array (including all memory array blockstacks) is 97.47%.

The Ys memory array stack yield is then multiplied by the yield of thecontroller Yc. Assuming a die size of less than 50 mm², a reasonable Ycfor a controller fabricated from a 0.5 cm BiCMOS or mixed signal processwould be between 65% and 85%, giving a net 3DS memory circuit yield ofbetween 63.4% and 82.8%. If a redundant controller circuit layer isadded to the 3DS memory stack, the yield probabilities would be between85.7% and 95.2%.

The effective yield of a memory array block can be further increased bythe optional use of ECC logic. ECC logic corrects data bit errors forsome group size of data bits. The syndrome bits necessary for theoperation of ECC logic would be stored on redundant gate-lines of any ofthe memory array layers in a vertically associated block stack. Further,if necessary, in order to accommodate the storage of ECC syndrome bits,additional memory array layers could be added to the circuit.

Advantageous 3DS Memory Device Controller Capabilities

As compared to a conventional memory circuit, the 3DS memory controllercircuit can have various advantageous capabilities due the additionalarea available for controller circuitry and the availability of variousmixed signal process fabrication technologies. Some of thesecapabilities are self-test of memory cells with dynamic gate-lineaddress assignment, virtual address translation, programmable addresswindowing or mapping, ECC, data compression and multi-level storage.

Dynamic gate-line address assignment is the use of programmable gates toenable the layer and gate-line for a read/write operation. This allowsthe physical order of memory storage to be separate or different fromthe logical order of stored memory.

The testing of each generation of memory devices has resulted insignificantly increased test costs. The 3DS memory controller reducesthe cost of testing by incorporating sufficient control logic to performan internal test (self-test) of the various memory array blocks. Circuittesting in the conventional ATE manner is required only for verificationof controller circuit functions. The scope of the internal test isfurther extended to the programmable (dynamic) assignment of uniqueaddresses corresponding to the various gate-lines of each memory arrayblock on each layer. Self-test capability of the 3DS controller circuitcan be used anytime during the life of the 3DS memory circuit as adiagnostic tool and as a means to increase circuit reliability byreconfiguring (sparing) the addresses of gate-lines that fail after the3DS memory circuit is in use in a product.

ECC is a circuit capability that, if included in the controller circuit,can be enabled or disabled by a programming signal or made a dedicatedfunction.

Data compression logic will allow the total amount of data that can bestored in the 3DS memory array to be increased. There are variousgenerally known data compression methods available for this purpose.

Larger sense amps allow greater dynamic performance and enable higherspeed read operations from the memory cells. Larger sense amps areexpected to provide the capability to store more than one bit(multi-level storage) of information in each memory cell; thiscapability has already been demonstrated in non-volatile memory circuitssuch as flash EPROM. Multi-level storage has also been proposed for usein the 4 Gbit DRAM generation circuits.

It will be appreciated by those of ordinary skill in the art that theinvention can be embodied in other specific forms without departing fromthe spirit or essential character thereof. The presently disclosedembodiments are therefore considered in all respects to be illustrativeand not restrictive. The scope of the invention is indicated by theappended claims rather than the foregoing description, and all changeswhich come within the meaning and range of equivalents thereof areintended to be embraced therein.

1. A stacked integrated circuit comprising: a logic layer includingmeans for initiating a memory access; at least one memory layer; and anarray of vertical interconnects between the logic layer and the at leastone memory layer for routing data vertically between the logic layer andselected storage locations within the at least one memory layer; whereinduring a single memory access cycle, a plurality of bytes of data arerouted from the selected storage locations to the logic layer.
 2. Theapparatus of claim 1, wherein said array is an array of verticalinterconnections interior to the stacked integrated circuit.
 3. Theapparatus of claim 1, wherein the logic layer comprises means forreceiving a virtual address and translating the virtual address to areal address.
 4. The apparatus of claim 1, wherein the logic layercomprises means for receiving an indirect address and translating theindirect address to one of a real address and a virtual address.
 5. Theapparatus of claim 1, wherein the at least one memory layer comprises atleast one content-addressable memory circuit, wherein the logic layerreceives a content word and produces as an output signal an address ofthe content word within the at least one memory circuit.
 6. Theapparatus of claim 1, wherein the logic layer comprises means forperforming at least one of audio encoding and audio decoding of datathat is one of read from and written to the memory layer.
 7. Theapparatus of claim 1, wherein the logic layer comprises means forperforming at least one of video encoding and video decoding of datathat is one of read from and written to the at least one memory layer.8. The apparatus of claim 1, wherein the logic layer comprises means forperforming recognition of data that is one of read from and written tothe at least one memory layer.
 9. The apparatus of claim 8, whereinrecognition processing is voice recognition processing.
 10. Theapparatus of claim 8, wherein recognition processing is hand writingrecognition processing.
 11. The apparatus of claim 1, wherein the logiclayer comprises means for performing power management functions.
 12. Theapparatus of claim 1, wherein the logic layer comprises means forperforming graphics acceleration functions.
 13. The apparatus of claim1, wherein the logic layer comprises means for performing databaseprocessing functions.
 14. The apparatus of claim 1, wherein the logiclayer comprises a microprocessor.
 15. The apparatus of claim 1, whereinthe logic layer is fabricated using one process technology, and the atleast one memory layer is fabricated using a different processtechnology.
 16. The apparatus of claim 15, wherein the different processtechnology is selected from a group consisting of: DRAM, SRAM, FLASH,EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
 17. Theapparatus of claim 1, wherein the at least one memory layer is formedfrom one of single crystal semiconductor material and polycrystallinesemiconductor material.
 18. A stacked integrated circuit memorycomprising: circuit layers having at least one logic layer and at leastone memory layer; and a plurality of connections interior to the stackedintegrated circuit memory for vertically routing data within the stackedintegrated circuit memory during a memory access.
 19. The apparatus ofclaim 18, wherein the at least one logic layer is a microprocessorlayer.
 20. The apparatus of claim 18, wherein the at least one logiclayer is a memory controller layer.
 21. The apparatus of claim 18,wherein the at least one logic layer performs programmable gate lineaddress assignment.
 22. The apparatus of claim 21, wherein theprogrammable gate-line address assignment provides for the use of atleast one redundant gate line.
 23. The apparatus of claim 18, whereinthe at least one logic layer can perform self test of at least one ofthe memory layers.
 24. The apparatus of claim 18, wherein at least oneof the at least one logic layer and the at least one memory layer ismade with polysilicon circuits.
 25. The apparatus of claim 18, whereinthe at least one logic layer is fabricated using a process technology,and the at least one memory layer is fabricated using a differentprocess technology.
 26. The apparatus of claim 25, wherein the at leastone memory layer is made with a process technology from a groupconsisting of: DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and GiantMagneto Resistance.
 27. The apparatus of claim 18, wherein the at leastone logic layer includes logic for performing at least one of thefollowing functions: virtual memory management, ECC, indirectaddressing, content addressing, data compression, data decompression,graphics acceleration, audio encoding, audio decoding, video encoding,video decoding, voice recognition, handwriting recognition, powermanagement and database processing.
 28. The apparatus of claim 1,wherein the logic layer and the memory layer are formed with one ofsingle crystal semiconductor material and polycrystalline semiconductormaterial.
 29. The apparatus of claim 1, wherein one of the logic layerand the memory layer is formed using a different process technology thananother of the logic layer and the memory layer, the different processtechnology being selected from a group consisting of DRAM, SRAM, FLASH,EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
 30. Theapparatus of claim 1, wherein at least one of the logic and the memorylayers comprises a microprocessor.
 31. The apparatus of claim 1, whereinthe logic layer performs testing of the at least one memory layer. 32.The apparatus of claim 1, wherein the at least one memory layer hasmultiple memory locations including at least one memory location usedfor sparing, wherein data from the at least one memory location on theat least one memory layer is used instead of data from a defectivememory location on the at least one memory layer.
 33. The apparatus ofclaim 1, wherein the logic layer performs programmable gate line addressassignment with respect to the at least one memory layer.
 34. Theapparatus of claim 1, wherein a plurality of interior verticalinterconnections traverse at least one of the layers.
 35. The apparatusof claim 1, wherein continuous vertical interconnections connectcircuitry of the layers.
 36. The apparatus of claim 1, whereininformation processing is performed on data routed between circuitry ontwo or more of the layers.
 37. The apparatus of claim 1, wherein atleast one of the layers has reconfiguration circuitry.
 38. The apparatusof claim 1, further comprising at least one logic layer having logic forperforming at least one of the following functions: virtual memorymanagement, ECC, indirect addressing, content addressing, datacompression, data decompression, graphics acceleration, audio encoding,audio decoding, video encoding, video decoding, voice recognition,handwriting recognition, power management and database processing. 39.The apparatus of claim 1, further comprising: a memory array having aplurality of memory cells, a plurality of data lines, and a plurality ofgate lines, each memory storage cell storing a data value and comprisingcircuitry for coupling that data value to one of said data lines inresponse to a gate control signal on one of said gate lines; circuitryfor generating a gate control signal in response to an address,including means for mapping addresses to gate lines; and a controllerfor determining that one of said memory cells is defective and foraltering said mapping to eliminate references to said one of said memorycells.
 40. The apparatus of claim 1, further comprising: one or morecontroller layers; one or more memory layers; a plurality of data linesand a plurality of gate lines on each memory layer; an array of memorycells on each memory layer, each memory cell storing a data value andcomprising circuitry for coupling that data value to one of said datalines in response to the selection of one of said gate lines; a gateline selection circuit for enabling a gate line for a memory operation,said gate line selection circuit comprising programmable gates toreceive address assignments for one or more of said gate lines, saidaddress assignments for determining which of said gate lines is selectedfor each programmed address assignment; and controller logic fordetermining that one of said array memory cells is defective and foraltering, in at least one instance, said address assignments of saidgate lines to eliminate references to that gate line that causes thatdefective memory cell to couple a data value to one of said data lines.41. The apparatus of claim 40, wherein said controller tests said memorycells periodically to determine if any of said memory cells is defectiveand wherein said controller eliminates references in said addressassignments to gate lines that cause said detected defective memorycells to couple data values to said data lines.
 42. The apparatus ofclaim 40, further comprising programmable logic to prevent the use ofdata values from data lines when gate lines cause said detecteddefective memory cells to couple data values to said data lines.
 43. Theapparatus of claim 40, wherein said memory cells are arranged withinphysical space in a physical order and are arranged within an addressspace in a logical order, wherein said physical order of at least onememory cell is different than the logical order of that memory cell. 44.The apparatus of claim 40, wherein external testing of the controllerportion of the apparatus together with testing by the controller of thememory cells achieves a functional testing of a preponderance of thememory cells.
 45. The apparatus of claim 40, wherein testing by thecontroller of the memory cells substantially reduces or eliminates theneed for external testing of the memory cells of the memory circuitlayers.
 46. The apparatus of claim 40, wherein altering said addressassignments comprises preventing the use of at least one defective gateline and replacing references to memory cells addressed using saiddefective gate line with references to spare memory cells addressedusing a spare gate line.
 47. The apparatus of claim 18, wherein thelogic layer and the memory layer are formed with one of single crystalsemiconductor material and polycrystalline semiconductor material. 48.The apparatus of claim 18, wherein one of the logic layer and the memorylayer is formed using a different process technology than another of thelogic layer and the memory layer, the different process technology beingselected from a group consisting of DRAM, SRAM, FLASH, EPROM,EEPROM/Ferroelectric and Giant Magneto Resistance.
 49. The apparatus ofclaim 18, wherein at least one of the logic and the memory layerscomprises a microprocessor.
 50. The apparatus of claim 18, wherein thelogic layer performs testing of the at least one memory layer.
 51. Theapparatus of claim 18, wherein the at least one memory layer hasmultiple memory locations including at least one memory location usedfor sparing, wherein data from the at least one memory location on theat least one memory layer is used instead of data from a defectivememory location on the at least one memory layer.
 52. The apparatus ofclaim 18, wherein the logic layer performs programmable gate lineaddress assignment with respect to the at least one memory layer. 53.The apparatus of claim 18, wherein a plurality of interior verticalinterconnections traverse at least one of the layers.
 54. The apparatusof claim 18, wherein continuous vertical interconnections connectcircuitry of the layers.
 55. The apparatus of claim 18, whereininformation processing is performed on data routed between circuitry ontwo or more of the layers.
 56. The apparatus of claim 18, wherein atleast one of the layers has reconfiguration circuitry.
 57. The apparatusof claim 18, further comprising at least one logic layer having logicfor performing at least one of the following functions: virtual memorymanagement, ECC, indirect addressing, content addressing, datacompression, data decompression, graphics acceleration, audio encoding,audio decoding, video encoding, video decoding, voice recognition,handwriting recognition, power management and database processing. 58.The apparatus of claim 18, further comprising: a memory array having aplurality of memory cells, a plurality of data lines, and a plurality ofgate lines, each memory storage cell storing a data value and comprisingcircuitry for coupling that data value to one of said data lines inresponse to a gate control signal on one of said gate lines; circuitryfor generating a gate control signal in response to an address,including means for mapping addresses to gate lines; and a controllerfor determining that one of said memory cells is defective and foraltering said mapping to eliminate references to said one of said memorycells.
 59. The apparatus of claim 18, further comprising: one or morecontroller layers; one or more memory layers; a plurality of data linesand a plurality of gate lines on each memory layer; an array of memorycells on each memory layer, each memory cell storing a data value andcomprising circuitry for coupling that data value to one of said datalines in response to the selection of one of said gate lines; a gateline selection circuit for enabling a gate line for a memory operation,said gate line selection circuit comprising programmable gates toreceive address assignments for one or more of said gate lines! saidaddress assignments for determining which of said gate lines is selectedfor each programmed address assignment; and controller logic fordetermining that one of said array memory cells is defective and foraltering! in at least one instance, said address assignments of saidgate lines to eliminate references to that gate line that causes thatdefective memory cell to couple a data value to one of said data lines.60. The apparatus of claim 59, wherein said controller tests said memorycells periodically to determine if any of said memory cells is defectiveand wherein said controller eliminates references in said addressassignments to gate lines that cause said detected defective memorycells to couple data values to said data lines.
 61. The apparatus ofclaim 59, further comprising programmable logic to prevent the use ofdata values from data lines when gate lines cause said detecteddefective memory cells to couple data values to said data lines.
 62. Theapparatus of claim 59, wherein said memory cells are arranged withinphysical space in a physical order and are arranged within an addressspace in a logical order, wherein said physical order of at least onememory cell is different than the logical order of that memory cell. 63.The apparatus of claim 59, wherein external testing of the controllerportion of the apparatus together with testing by the controller of thememory cells achieves a functional testing of a preponderance of thememory cells.
 64. The apparatus of claim 59, wherein testing by thecontroller of the memory cells substantially reduces or eliminates theneed for external testing of the memory cells of the memory circuitlayers.
 65. The apparatus of claim 59, wherein altering said addressassignments comprises preventing the use of at least one defective gateline and replacing references to memory cells addressed using saiddefective gate line with references to spare memory cells addressedusing a spare gate line.
 66. An information processing integratedcircuit comprising: stacked integrated circuit layers having a logiclayer and a memory layer; and logic on the logic layer for initiating amemory access; wherein vertical interconnections route data of thememory access interior to the stacked integrated circuit layers betweenthe logic layer and at least one memory location on the a memory layer.67. The apparatus of claim 66, wherein the logic layer and the memorylayer are formed with one of single crystal semiconductor material andpolycrystalline semiconductor material.
 68. The apparatus of claim 66,wherein one of the logic layer and the memory layer is formed using adifferent process technology than another of the logic layer and thememory layer, the different process technology being selected from agroup consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric andGiant Magneto Resistance.
 69. The apparatus of claim 66, wherein atleast one of the logic and the memory layers comprises a microprocessor.70. The apparatus of claim 66, wherein the logic layer performs testingof the at least one memory layer.
 71. The apparatus of claim 66, whereinthe at least one memory layer has multiple memory locations including atleast one memory location used for sparing, wherein data from the atleast one memory location on the at least one memory layer is usedinstead of data from a defective memory location on the at least onememory layer.
 72. The apparatus of claim 66, wherein the logic layerperforms programmable gate line address assignment with respect to theat least one memory layer.
 73. The apparatus of claim 66, wherein aplurality of interior vertical interconnections traverse at least one ofthe layers.
 74. The apparatus of claim 66, wherein continuous verticalinterconnections connect circuitry of the layers.
 75. The apparatus ofclaim 66, wherein information processing is performed on data routedbetween circuitry on two or more of the layers.
 76. The apparatus ofclaim 66, wherein at least one of the layers has reconfigurationcircuitry.
 77. The apparatus of claim 66, further comprising at leastone logic layer having logic for performing at least one of thefollowing functions: virtual memory management, ECC, indirectaddressing, content addressing, data compression, data decompression,graphics acceleration, audio encoding, audio decoding, video encoding,video decoding, voice recognition, handwriting recognition, powermanagement and database processing.
 78. The apparatus of claim 66,further comprising: a memory array having a plurality of memory cells, aplurality of data lines, and a plurality of gate lines, each memorystorage cell storing a data value and comprising circuitry for couplingthat data value to one of said data lines in response to a gate controlsignal on one of said gate lines; circuitry for generating a gatecontrol signal in response to an address, including means for mappingaddresses to gate lines; and a controller for determining that one ofsaid memory cells is defective and for altering said mapping toeliminate references to said one of said memory cells.
 79. The apparatusof claim 66, further comprising: one or more controller layers; one ormore memory layers; a plurality of data lines and a plurality of gatelines on each memory layer; an array of memory cells on each memorylayer, each memory cell storing a data value and comprising circuitryfor coupling that data value to one of said data lines in response tothe selection of one of said gate lines; a gate line selection circuitfor enabling a gate line for a memory operation, said gate lineselection circuit comprising programmable gates to receive addressassignments for one or more of said gate lines, said address assignmentsfor determining which of said gate lines is selected for each programmedaddress assignment; and controller logic for determining that one ofsaid array memory cells is defective and for altering, in at least oneinstance, said address assignments of said gate lines to eliminatereferences to that gate line that causes that defective memory cell tocouple a data value to one of said data lines.
 80. The apparatus ofclaim 79, wherein said controller tests said memory cells periodicallyto determine if any of said memory cells is defective and wherein saidcontroller eliminates references in said address assignments to gatelines that cause said detected defective memory cells to couple datavalues to said data lines.
 81. The apparatus of claim 79, furthercomprising programmable logic to prevent the use of data values fromdata lines when gate lines cause said detected defective memory cells tocouple data values to said data lines.
 82. The apparatus of claim 79,wherein said memory cells are arranged within physical space in aphysical order and are arranged within an address space in a logicalorder, wherein said physical order of at least one memory cell isdifferent than the logical order of that memory cell.
 83. The apparatusof claim 79, wherein external testing of the controller portion of theapparatus together with testing by the controller of the memory cellsachieves a functional testing of a preponderance of the memory cells.84. The apparatus of claim 79, wherein testing by the controller of thememory cells substantially reduces or eliminates the need for externaltesting of the memory cells of the memory circuit layers.
 85. Theapparatus of claim 79, wherein altering said address assignmentscomprises preventing the use of at least one defective gate line andreplacing references to memory cells addressed using said defective gateline with references to spare memory cells addressed using a spare gateline.
 86. An information processing integrated circuit comprising:stacked integrated circuit layers having a logic layer and a memorylayer; and a plurality of vertical interconnections interior to thestacked integrated circuit layers for the transfer of data between thelogic layer and the memory circuit layer of said information processingintegrated circuit.
 87. The apparatus of claim 86, wherein the logiclayer and the memory layer are formed with one of single crystalsemiconductor material and polycrystalline semiconductor material. 88.The apparatus of claim 86, wherein one of the logic layer and the memorylayer is formed using a different process technology than another of thelogic layer and the memory layer, the different process technology beingselected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM,Ferroelectric and Giant Magneto Resistance.
 89. The apparatus of claim86, wherein at least one of the logic and the memory layers comprises amicroprocessor.
 90. The apparatus of claim 86, wherein the logic layerperforms testing of the at least one memory layer.
 91. The apparatus ofclaim 86, wherein the at least one memory layer has multiple memorylocations including at least one memory location used for sparing,wherein data from the at least one memory location on the at least onememory layer is used instead of data from a defective memory location onthe at least one memory layer.
 92. The apparatus of claim 86, whereinthe logic layer performs programmable gate line address assignment withrespect to the at least one memory layer.
 93. The apparatus of claim 86,wherein a plurality of interior vertical interconnections traverse atleast one of the layers.
 94. The apparatus of claim 86, whereincontinuous vertical interconnections connect circuitry of the layers.95. The apparatus of claim 86, wherein information processing isperformed on data routed between circuitry on two or more of the layers.96. The apparatus of claim 86, wherein at least one of the layers hasreconfiguration circuitry.
 97. The apparatus of claim 86, furthercomprising at least one logic layer having logic for performing at leastone of the following functions: virtual memory management, ECC, indirectaddressing, content addressing, data compression, data decompression,graphics acceleration, audio encoding, audio decoding, video encoding,video decoding, voice recognition, handwriting recognition, powermanagement and database processing.
 98. The apparatus of claim 86,further comprising: a memory array having a plurality of memory cells, aplurality of data lines, and a plurality of gate lines, each memorystorage cell storing a data value and comprising circuitry for couplingthat data value to one of said data lines in response to a gate controlsignal on one of said gate lines; circuitry for generating a gatecontrol signal in response to an address, including means for mappingaddresses to gate lines; and a controller for determining that one ofsaid memory cells is defective and for altering said mapping toeliminate references to said one of said memory cells.
 99. The apparatusof claim 86, further comprising: one or more controller layers; one ormore memory layers; a plurality of data lines and a plurality of gatelines on each memory layer; an array of memory cells on each memorylayer, each memory cell storing a data value and comprising circuitryfor coupling that data value to one of said data lines in response tothe selection of one of said gate lines; a gate line selection circuitfor enabling a gate line for a memory operation, said gate lineselection circuit comprising programmable gates to receive addressassignments for one or more of said gate lines, said address assignmentsfor determining which of said gate lines is selected for each programmedaddress assignment; and controller logic for determining that one ofsaid array memory cells is defective and for altering, in at least oneinstance, said address assignments of said gate lines to eliminatereferences to that gate line that causes that defective memory cell tocouple a data value to one of said data lines.
 100. The apparatus ofclaim 99, wherein said controller tests said memory cells periodicallyto determine if any of said memory cells is defective and wherein saidcontroller eliminates references in said address assignments to gatelines that cause said detected defective memory cells to couple datavalues to said data lines.
 101. The apparatus of claim 99, furthercomprising programmable logic to prevent the use of data values fromdata lines when gate lines cause said detected defective memory cells tocouple data values to said data lines.
 102. The apparatus of claim 99,wherein said memory cells are arranged within physical space in aphysical order and are arranged within an address space in a logicalorder, wherein said physical order of at least one memory cell isdifferent than the logical order of that memory cell.
 103. The apparatusof claim 99, wherein external testing of the controller portion of theapparatus together with testing by the controller of the memory cellsachieves a functional testing of a preponderance of the memory cells.104. The apparatus of claim 99, wherein testing by the controller of thememory cells substantially reduces or eliminates the need for externaltesting of the memory cells of the memory circuit layers.
 105. Theapparatus of claim 99, wherein altering said address assignmentscomprises preventing the use of at least one defective gate line andreplacing references to memory cells addressed using said defective gateline with references to spare memory cells addressed using a spare gateline.
 106. An integrated circuit comprising: stacked integrated circuitlayers having a logic layer and a memory layer; and verticalinterconnections interior to the integrated circuit with at least one ofthe vertical interconnections formed through the memory layer of saidintegrated circuit.
 107. The apparatus of claim 106, wherein the logiclayer and the memory layer are formed with one of single crystalsemiconductor material and polycrystalline semiconductor material. 108.The apparatus of claim 106, wherein one of the logic layer and thememory layer is formed using a different process technology than anotherof the logic layer and the memory layer, the different processtechnology being selected from a group consisting of DRAM, SRAM, FLASH,EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
 109. Theapparatus of claim 106, wherein at least one of the logic and the memorylayers comprises a microprocessor.
 110. The apparatus of claim 106,wherein the logic layer performs testing of the at least one memorylayer.
 111. The apparatus of claim 106, wherein the at least one memorylayer has multiple memory locations including at least one memorylocation used for sparing, wherein data from the at least one memorylocation on the at least one memory layer is used instead of data from adefective memory location on the at least one memory layer.
 112. Theapparatus of claim 106, wherein the logic layer performs programmablegate line address assignment with respect to the at least one memorylayer.
 113. The apparatus of claim 106, wherein a plurality of interiorvertical interconnections traverse at least one of the layers.
 114. Theapparatus of claim 106, wherein continuous vertical interconnectionsconnect circuitry of the layers.
 115. The apparatus of claim 106,wherein information processing is performed on data routed betweencircuitry on two or more of the layers.
 116. The apparatus of claim 106,wherein at least one of the layers has reconfiguration circuitry. 117.The apparatus of claim 106, further comprising at least one logic layerhaving logic for performing at least one of the following functions:virtual memory management, ECC, indirect addressing, content addressing,data compression, data decompression, graphics acceleration, audioencoding, audio decoding, video encoding, video decoding, voicerecognition, handwriting recognition, power management and databaseprocessing.
 118. The apparatus of claim 106, further comprising: amemory array having a plurality of memory cells, a plurality of datalines, and a plurality of gate lines, each memory storage cell storing adata value and comprising circuitry for coupling that data value to oneof said data lines in response to a gate control signal on one of saidgate lines; circuitry for generating a gate control signal in responseto an address, including means for mapping addresses to gate lines; anda controller for determining that one of said memory cells is defectiveand for altering said mapping to eliminate references to said one ofsaid memory cells.
 119. The apparatus of claim 106, further comprising:one or more controller layers; one or more memory layers; a plurality ofdata lines and a plurality of gate lines on each memory layer; an arrayof memory cells on each memory layer, each memory cell storing a datavalue and comprising circuitry for coupling that data value to one ofsaid data lines in response to the selection of one of said gate lines;a gate line selection circuit for enabling a gate line for a memoryoperation, said gate line selection circuit comprising programmablegates to receive address assignments for one or more of said gate lines,said address assignments for determining which of said gate lines isselected for each programmed address assignment; and controller logicfor determining that one of said array memory cells is defective and foraltering, in at least one instance, said address assignments of saidgate lines to eliminate references to that gate line that causes thatdefective memory cell to couple a data value to one of said data lines.120. The apparatus of claim 119, wherein said controller tests saidmemory cells periodically to determine if any of said memory cells isdefective and wherein said controller eliminates references in saidaddress assignments to gate lines that cause said detected defectivememory cells to couple data values to said data lines.
 121. Theapparatus of claim 119, further comprising programmable logic to preventthe use of data values from data lines when gate lines cause saiddetected defective memory cells to couple data values to said datalines.
 122. The apparatus of claim 119, wherein said memory cells arearranged within physical space in a physical order and are arrangedwithin an address space in a logical order, wherein said physical orderof at least one memory cell is different than the logical order of thatmemory cell.
 123. The apparatus of claim 119, wherein external testingof the controller portion of the apparatus together with testing by thecontroller of the memory cells achieves a functional testing of apreponderance of the memory cells.
 124. The apparatus of claim 119,wherein testing by the controller of the memory cells substantiallyreduces or eliminates the need for external testing of the memory cellsof the memory circuit layers.
 125. The apparatus of claim 119, whereinaltering said address assignments comprises preventing the use of atleast one defective gate line and replacing references to memory cellsaddressed using said defective gate line with references to spare memorycells addressed using a spare gate line.
 126. The apparatus of claim 66,wherein the logic layer is fabricated using one process technology, andthe memory layer is fabricated using a different process technology.127. The apparatus of claim 86, wherein the logic layer is fabricatedusing one process technology, and the memory layer is fabricated using adifferent process technology.
 128. The apparatus of claim 106, whereinthe logic layer is fabricated using one process technology, and thememory layer is fabricated using a different process technology. 129.The apparatus of claim 1, wherein at least one of the layers has athickness of one of 10 microns or less and 50 microns or less.
 130. Theapparatus of claim 1, wherein at least one of the layers is formed witha low stress dielectric, wherein the low stress dielectric is at leastone of a silicon dioxide dielectric and an oxide of silicon dielectricand is caused to have a tensile stress of about 5×10⁸ dynes/cm² or less.131. The apparatus of claim 18, wherein at least one of the layers has athickness of one of 10 microns or less and 50 microns or less.
 132. Theapparatus of claim 18, wherein at least one of the layers is formed witha low stress dielectric, wherein the low stress dielectric is at leastone of a silicon dioxide dielectric and an oxide of silicon dielectricand is caused to have a tensile stress of about 5×10⁸ dynes/cm² or less.133. The apparatus of claim 66, wherein at least one of the layers has athickness of one of 10 microns or less and 50 microns or less.
 134. Theapparatus of claim 66, wherein at least one of the layers is formed witha low stress dielectric, wherein the low stress dielectric is at leastone of a silicon dioxide dielectric and an oxide of silicon dielectricand is caused to have a tensile stress of about 5×10⁸ dynes/cm² or less.135. The apparatus of claim 86, wherein at least one of the layers has athickness of one of 10 microns or less and 50 microns or less.
 136. Theapparatus of claim 86, wherein at least one of the layers is formed witha low stress dielectric, wherein the low stress dielectric is at leastone of a silicon dioxide dielectric and an oxide of silicon dielectricand is caused to have a tensile stress of about 5×10⁸ dynes/cm² or less.137. The apparatus of claim 106, wherein at least one of the layers hasa thickness of one of 10 microns or less and 50 microns or less. 138.The apparatus of claim 106, wherein at least one of the layers is formedwith a low stress dielectric, wherein the low stress dielectric is atleast one of a silicon dioxide dielectric and an oxide of silicondielectric and is caused to have a tensile stress of about 5×10⁸dynes/cm² or less.